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Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] - Rev 76

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 3797d 21h /i2c/trunk/rtl/
75 Fixed sSDA generation rherveille 3803d 17h /i2c/trunk/rtl/
74 Added SCL/SDA line filter rherveille 3942d 14h /i2c/trunk/rtl/
73 Fixed double wishbone write in a single access rherveille 3942d 14h /i2c/trunk/rtl/
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 3942d 14h /i2c/trunk/rtl/
71 Fixed double wishbone write in a single access rherveille 3942d 14h /i2c/trunk/rtl/
68 New directory structure. root 4251d 08h /i2c/trunk/rtl/
67 Fixed slave_wait clocked event syntax rherveille 4284d 10h /trunk/rtl/
66 Fixed type iscl_oen instead of scl_oen rherveille 4299d 10h /trunk/rtl/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4299d 20h /trunk/rtl/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4299d 20h /trunk/rtl/
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4299d 20h /trunk/rtl/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4300d 10h /trunk/rtl/
60 Added missing semicolons ';' on endif rherveille 5131d 18h /trunk/rtl/
59 fixed short scl high pulse after clock stretch rherveille 5136d 20h /trunk/rtl/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5168d 21h /trunk/rtl/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 5722d 21h /trunk/rtl/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6018d 19h /trunk/rtl/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6018d 19h /trunk/rtl/
51 Fixed simulation issue when writing to CR register rherveille 6072d 20h /trunk/rtl/

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