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[/] [i2c/] [trunk/] [rtl/] - Rev 36

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Rev Log message Author Age Path
36 Fixed cmd_ack generation item (no bug). rherveille 7729d 11h /i2c/trunk/rtl/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7763d 01h /i2c/trunk/rtl/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7767d 00h /i2c/trunk/rtl/
33 Fixed a bug in the Command Register declaration. rherveille 7789d 09h /i2c/trunk/rtl/
31 Core is now a Multimaster I2C controller. rherveille 7803d 09h /i2c/trunk/rtl/
30 Small code simplifications rherveille 7803d 09h /i2c/trunk/rtl/
29 Core is now a Multimaster I2C controller rherveille 7803d 11h /i2c/trunk/rtl/
28 *** empty log message *** rherveille 7829d 03h /i2c/trunk/rtl/
27 Cleaned up code rherveille 7829d 03h /i2c/trunk/rtl/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7860d 07h /i2c/trunk/rtl/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7997d 18h /i2c/trunk/rtl/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8214d 15h /i2c/trunk/rtl/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8219d 14h /i2c/trunk/rtl/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8219d 14h /i2c/trunk/rtl/
13 Fixed some synthesis warnings. rherveille 8230d 18h /i2c/trunk/rtl/
11 Changed RST_LVL define to parameter. rherveille 8239d 17h /i2c/trunk/rtl/
10 Created new directory structure.
Added Verilog version.		 rherveille 8261d 13h /i2c/trunk/rtl/

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