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Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] - Rev 51

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Rev	Log message	Author	Age	Path
51	Fixed simulation issue when writing to CR register	rherveille	7363d 19h	/i2c/trunk/rtl/
48	Fixed a bug in the arbitration-lost signal generation. VHDL version only.	rherveille	7379d 21h	/i2c/trunk/rtl/
47	Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.	rherveille	7388d 18h	/i2c/trunk/rtl/
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7558d 19h	/i2c/trunk/rtl/
39	Forgot an 'end if' :-/	rherveille	7578d 15h	/i2c/trunk/rtl/
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7581d 22h	/i2c/trunk/rtl/
36	Fixed cmd_ack generation item (no bug).	rherveille	7733d 15h	/i2c/trunk/rtl/
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7767d 05h	/i2c/trunk/rtl/
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7771d 03h	/i2c/trunk/rtl/
33	Fixed a bug in the Command Register declaration.	rherveille	7793d 13h	/i2c/trunk/rtl/
31	Core is now a Multimaster I2C controller.	rherveille	7807d 13h	/i2c/trunk/rtl/
30	Small code simplifications	rherveille	7807d 13h	/i2c/trunk/rtl/
29	Core is now a Multimaster I2C controller	rherveille	7807d 14h	/i2c/trunk/rtl/
28	* empty log message *	rherveille	7833d 07h	/i2c/trunk/rtl/
27	Cleaned up code	rherveille	7833d 07h	/i2c/trunk/rtl/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7864d 11h	/i2c/trunk/rtl/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8001d 22h	/i2c/trunk/rtl/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8218d 18h	/i2c/trunk/rtl/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8223d 17h	/i2c/trunk/rtl/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8223d 17h	/i2c/trunk/rtl/
13	Fixed some synthesis warnings.	rherveille	8234d 21h	/i2c/trunk/rtl/
11	Changed RST_LVL define to parameter.	rherveille	8243d 20h	/i2c/trunk/rtl/
10	Created new directory structure. Added Verilog version.	rherveille	8265d 17h	/i2c/trunk/rtl/

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[/] [i2c/] [trunk/] [rtl/] - Rev 51

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