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[/] [i2c/] [trunk/] [rtl/] - Rev 57

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Rev Log message Author Age Path
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6468d 06h /i2c/trunk/rtl/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7022d 05h /i2c/trunk/rtl/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7318d 03h /i2c/trunk/rtl/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7318d 04h /i2c/trunk/rtl/
51 Fixed simulation issue when writing to CR register rherveille 7372d 04h /i2c/trunk/rtl/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7388d 07h /i2c/trunk/rtl/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7397d 03h /i2c/trunk/rtl/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7567d 04h /i2c/trunk/rtl/
39 Forgot an 'end if' :-/ rherveille 7587d 00h /i2c/trunk/rtl/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7590d 08h /i2c/trunk/rtl/
36 Fixed cmd_ack generation item (no bug). rherveille 7742d 00h /i2c/trunk/rtl/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7775d 15h /i2c/trunk/rtl/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7779d 13h /i2c/trunk/rtl/
33 Fixed a bug in the Command Register declaration. rherveille 7801d 22h /i2c/trunk/rtl/
31 Core is now a Multimaster I2C controller. rherveille 7815d 23h /i2c/trunk/rtl/
30 Small code simplifications rherveille 7815d 23h /i2c/trunk/rtl/
29 Core is now a Multimaster I2C controller rherveille 7816d 00h /i2c/trunk/rtl/
28 *** empty log message *** rherveille 7841d 16h /i2c/trunk/rtl/
27 Cleaned up code rherveille 7841d 16h /i2c/trunk/rtl/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7872d 20h /i2c/trunk/rtl/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8010d 07h /i2c/trunk/rtl/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8227d 04h /i2c/trunk/rtl/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.		 rherveille 8232d 03h /i2c/trunk/rtl/
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.		 rherveille 8232d 03h /i2c/trunk/rtl/
13 Fixed some synthesis warnings. rherveille 8243d 07h /i2c/trunk/rtl/
11 Changed RST_LVL define to parameter. rherveille 8252d 06h /i2c/trunk/rtl/
10 Created new directory structure.
Added Verilog version.		 rherveille 8274d 02h /i2c/trunk/rtl/

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