URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] - Rev 66

Rev	Log message	Author	Age	Path
33	Fixed a bug in the Command Register declaration.	rherveille	7789d 17h	/i2c/trunk/rtl/
31	Core is now a Multimaster I2C controller.	rherveille	7803d 18h	/i2c/trunk/rtl/
30	Small code simplifications	rherveille	7803d 18h	/i2c/trunk/rtl/
29	Core is now a Multimaster I2C controller	rherveille	7803d 19h	/i2c/trunk/rtl/
28	* empty log message *	rherveille	7829d 11h	/i2c/trunk/rtl/
27	Cleaned up code	rherveille	7829d 12h	/i2c/trunk/rtl/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7860d 16h	/i2c/trunk/rtl/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7998d 02h	/i2c/trunk/rtl/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8214d 23h	/i2c/trunk/rtl/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8219d 22h	/i2c/trunk/rtl/