OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] - Rev 76

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 5098d 23h /i2c/trunk/rtl
75 Fixed sSDA generation rherveille 5104d 20h /i2c/trunk/rtl
74 Added SCL/SDA line filter rherveille 5243d 16h /i2c/trunk/rtl
73 Fixed double wishbone write in a single access rherveille 5243d 16h /i2c/trunk/rtl
72 Fixed AL generation
Added median filter on SDA and SCL inputs		 rherveille 5243d 17h /i2c/trunk/rtl
71 Fixed double wishbone write in a single access rherveille 5243d 17h /i2c/trunk/rtl
68 New directory structure. root 5552d 11h /i2c/trunk/rtl
67 Fixed slave_wait clocked event syntax rherveille 5585d 13h /trunk/rtl
66 Fixed type iscl_oen instead of scl_oen rherveille 5600d 12h /trunk/rtl
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5600d 22h /trunk/rtl
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation		 rherveille 5600d 22h /trunk/rtl
63 Added clock synchronization logic
Fixed slave_wait signal		 rherveille 5600d 23h /trunk/rtl
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits		 rherveille 5601d 13h /trunk/rtl
60 Added missing semicolons ';' on endif rherveille 6432d 21h /trunk/rtl
59 fixed short scl high pulse after clock stretch rherveille 6437d 22h /trunk/rtl
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal		 rherveille 6470d 00h /trunk/rtl
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.		 rherveille 7024d 00h /trunk/rtl
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7319d 21h /trunk/rtl
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7319d 22h /trunk/rtl
51 Fixed simulation issue when writing to CR register rherveille 7373d 23h /trunk/rtl
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7390d 01h /trunk/rtl
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7398d 21h /trunk/rtl
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7568d 22h /trunk/rtl
39 Forgot an 'end if' :-/ rherveille 7588d 18h /trunk/rtl
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7592d 02h /trunk/rtl
36 Fixed cmd_ack generation item (no bug). rherveille 7743d 19h /trunk/rtl
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7777d 09h /trunk/rtl
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7781d 07h /trunk/rtl
33 Fixed a bug in the Command Register declaration. rherveille 7803d 16h /trunk/rtl
31 Core is now a Multimaster I2C controller. rherveille 7817d 17h /trunk/rtl

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.