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[/] [i2c/] [trunk/] [rtl/] - Rev 76

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 5078d 13h /i2c/trunk/rtl
75 Fixed sSDA generation rherveille 5084d 10h /i2c/trunk/rtl
74 Added SCL/SDA line filter rherveille 5223d 07h /i2c/trunk/rtl
73 Fixed double wishbone write in a single access rherveille 5223d 07h /i2c/trunk/rtl
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 5223d 07h /i2c/trunk/rtl
71 Fixed double wishbone write in a single access rherveille 5223d 07h /i2c/trunk/rtl
68 New directory structure. root 5532d 01h /i2c/trunk/rtl
67 Fixed slave_wait clocked event syntax rherveille 5565d 03h /trunk/rtl
66 Fixed type iscl_oen instead of scl_oen rherveille 5580d 02h /trunk/rtl
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5580d 12h /trunk/rtl
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5580d 13h /trunk/rtl
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5580d 13h /trunk/rtl
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5581d 03h /trunk/rtl
60 Added missing semicolons ';' on endif rherveille 6412d 11h /trunk/rtl
59 fixed short scl high pulse after clock stretch rherveille 6417d 12h /trunk/rtl
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6449d 14h /trunk/rtl
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 7003d 14h /trunk/rtl
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7299d 11h /trunk/rtl
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7299d 12h /trunk/rtl
51 Fixed simulation issue when writing to CR register rherveille 7353d 13h /trunk/rtl

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