URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] - Rev 36

Rev	Log message	Author	Age	Path
36	Fixed cmd_ack generation item (no bug).	rherveille	7724d 23h	/i2c/trunk/rtl/verilog/
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7758d 13h	/i2c/trunk/rtl/verilog/
33	Fixed a bug in the Command Register declaration.	rherveille	7784d 20h	/i2c/trunk/rtl/verilog/
30	Small code simplifications	rherveille	7798d 21h	/i2c/trunk/rtl/verilog/
29	Core is now a Multimaster I2C controller	rherveille	7798d 22h	/i2c/trunk/rtl/verilog/
27	Cleaned up code	rherveille	7824d 15h	/i2c/trunk/rtl/verilog/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7855d 19h	/i2c/trunk/rtl/verilog/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7993d 05h	/i2c/trunk/rtl/verilog/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8210d 02h	/i2c/trunk/rtl/verilog/
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8215d 01h	/i2c/trunk/rtl/verilog/
13	Fixed some synthesis warnings.	rherveille	8226d 05h	/i2c/trunk/rtl/verilog/
11	Changed RST_LVL define to parameter.	rherveille	8235d 04h	/i2c/trunk/rtl/verilog/
10	Created new directory structure. Added Verilog version.	rherveille	8257d 01h	/i2c/trunk/rtl/verilog/