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[/] [i2c/] [trunk/] [rtl/] [verilog/] - Rev 71

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Rev	Log message	Author	Age	Path
68	New directory structure.	root	5548d 08h	/i2c/trunk/rtl/verilog
63	Added clock synchronization logic Fixed slave_wait signal	rherveille	5596d 20h	/i2c/trunk/rtl/verilog
62	Fixed synopsys miss spell (synopsis) Fixed cr[0] register width Fixed ! usage instead of ~ Fixed bit controller parameter width to 18bits	rherveille	5597d 10h	/i2c/trunk/rtl/verilog
57	fixed short scl high pulse after clock stretch fixed slave model not returning correct '(n)ack' signal	rherveille	6465d 21h	/i2c/trunk/rtl/verilog
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	7019d 21h	/i2c/trunk/rtl/verilog
52	Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit.	rherveille	7315d 19h	/i2c/trunk/rtl/verilog
47	Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command.	rherveille	7394d 18h	/i2c/trunk/rtl/verilog
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7564d 20h	/i2c/trunk/rtl/verilog
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7587d 23h	/i2c/trunk/rtl/verilog
36	Fixed cmd_ack generation item (no bug).	rherveille	7739d 16h	/i2c/trunk/rtl/verilog
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7773d 06h	/i2c/trunk/rtl/verilog
33	Fixed a bug in the Command Register declaration.	rherveille	7799d 13h	/i2c/trunk/rtl/verilog
30	Small code simplifications	rherveille	7813d 14h	/i2c/trunk/rtl/verilog
29	Core is now a Multimaster I2C controller	rherveille	7813d 15h	/i2c/trunk/rtl/verilog
27	Cleaned up code	rherveille	7839d 08h	/i2c/trunk/rtl/verilog
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7870d 12h	/i2c/trunk/rtl/verilog
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8007d 22h	/i2c/trunk/rtl/verilog
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8224d 19h	/i2c/trunk/rtl/verilog
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8229d 18h	/i2c/trunk/rtl/verilog
13	Fixed some synthesis warnings.	rherveille	8240d 22h	/i2c/trunk/rtl/verilog

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[/] [i2c/] [trunk/] [rtl/] [verilog/] - Rev 71

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