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[/] [i2c/] [trunk/] [rtl/] [verilog/] - Rev 75


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Rev Log message Author Age Path
74 Added SCL/SDA line filter rherveille 4893d 10h /i2c/trunk/rtl/verilog/
73 Fixed double wishbone write in a single access rherveille 4893d 10h /i2c/trunk/rtl/verilog/
68 New directory structure. root 5202d 04h /i2c/trunk/rtl/verilog/
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5250d 16h /i2c/trunk/rtl/verilog/
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5251d 06h /i2c/trunk/rtl/verilog/
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6119d 17h /i2c/trunk/rtl/verilog/
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6673d 17h /i2c/trunk/rtl/verilog/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6969d 15h /i2c/trunk/rtl/verilog/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7048d 15h /i2c/trunk/rtl/verilog/
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7218d 16h /i2c/trunk/rtl/verilog/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7241d 19h /i2c/trunk/rtl/verilog/
36 Fixed cmd_ack generation item (no bug). rherveille 7393d 12h /i2c/trunk/rtl/verilog/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7427d 02h /i2c/trunk/rtl/verilog/
33 Fixed a bug in the Command Register declaration. rherveille 7453d 10h /i2c/trunk/rtl/verilog/
30 Small code simplifications rherveille 7467d 10h /i2c/trunk/rtl/verilog/
29 Core is now a Multimaster I2C controller rherveille 7467d 11h /i2c/trunk/rtl/verilog/
27 Cleaned up code rherveille 7493d 04h /i2c/trunk/rtl/verilog/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7524d 08h /i2c/trunk/rtl/verilog/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7661d 19h /i2c/trunk/rtl/verilog/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7878d 15h /i2c/trunk/rtl/verilog/

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