URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_bit_ctrl.v] - Rev 36

Rev	Log message	Author	Age	Path
36	Fixed cmd_ack generation item (no bug).	rherveille	7738d 18h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7772d 08h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
30	Small code simplifications	rherveille	7812d 16h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
29	Core is now a Multimaster I2C controller	rherveille	7812d 17h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
27	Cleaned up code	rherveille	7838d 10h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7869d 14h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8007d 01h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8228d 20h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
10	Created new directory structure. Added Verilog version.	rherveille	8270d 20h	/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v