URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Rev 30

Rev	Log message	Author	Age	Path
30	Small code simplifications	rherveille	7813d 03h	/i2c/trunk/rtl/verilog/i2c_master_top.v
29	Core is now a Multimaster I2C controller	rherveille	7813d 04h	/i2c/trunk/rtl/verilog/i2c_master_top.v
27	Cleaned up code	rherveille	7838d 21h	/i2c/trunk/rtl/verilog/i2c_master_top.v
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8224d 09h	/i2c/trunk/rtl/verilog/i2c_master_top.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8229d 07h	/i2c/trunk/rtl/verilog/i2c_master_top.v
13	Fixed some synthesis warnings.	rherveille	8240d 11h	/i2c/trunk/rtl/verilog/i2c_master_top.v
11	Changed RST_LVL define to parameter.	rherveille	8249d 11h	/i2c/trunk/rtl/verilog/i2c_master_top.v
10	Created new directory structure. Added Verilog version.	rherveille	8271d 07h	/i2c/trunk/rtl/verilog/i2c_master_top.v