URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Rev 55

Rev	Log message	Author	Age	Path
55	Fixed register overwrite issue. Removed full_case pragma, replaced it by a default statement.	rherveille	7023d 08h	/i2c/trunk/rtl/verilog/i2c_master_top.v
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7568d 07h	/i2c/trunk/rtl/verilog/i2c_master_top.v
33	Fixed a bug in the Command Register declaration.	rherveille	7803d 01h	/i2c/trunk/rtl/verilog/i2c_master_top.v
30	Small code simplifications	rherveille	7817d 02h	/i2c/trunk/rtl/verilog/i2c_master_top.v
29	Core is now a Multimaster I2C controller	rherveille	7817d 03h	/i2c/trunk/rtl/verilog/i2c_master_top.v
27	Cleaned up code	rherveille	7842d 19h	/i2c/trunk/rtl/verilog/i2c_master_top.v
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8228d 07h	/i2c/trunk/rtl/verilog/i2c_master_top.v
14	Fixed wb_ack_o generation bug. Fixed bug in the byte_controller statemachine. Added headers.	rherveille	8233d 06h	/i2c/trunk/rtl/verilog/i2c_master_top.v
13	Fixed some synthesis warnings.	rherveille	8244d 10h	/i2c/trunk/rtl/verilog/i2c_master_top.v
11	Changed RST_LVL define to parameter.	rherveille	8253d 09h	/i2c/trunk/rtl/verilog/i2c_master_top.v
10	Created new directory structure. Added Verilog version.	rherveille	8275d 05h	/i2c/trunk/rtl/verilog/i2c_master_top.v