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[/] [i2c/] [trunk/] [rtl/] [verilog/] [i2c_master_top.v] - Rev 75


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Rev Log message Author Age Path
73 Fixed double wishbone write in a single access rherveille 5006d 15h /i2c/trunk/rtl/verilog/i2c_master_top.v
68 New directory structure. root 5315d 09h /i2c/trunk/rtl/verilog/i2c_master_top.v
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5364d 12h /i2c/trunk/rtl/verilog/i2c_master_top.v
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6786d 23h /i2c/trunk/rtl/verilog/i2c_master_top.v
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7331d 21h /i2c/trunk/rtl/verilog/i2c_master_top.v
33 Fixed a bug in the Command Register declaration. rherveille 7566d 15h /i2c/trunk/rtl/verilog/i2c_master_top.v
30 Small code simplifications rherveille 7580d 16h /i2c/trunk/rtl/verilog/i2c_master_top.v
29 Core is now a Multimaster I2C controller rherveille 7580d 17h /i2c/trunk/rtl/verilog/i2c_master_top.v
27 Cleaned up code rherveille 7606d 10h /i2c/trunk/rtl/verilog/i2c_master_top.v
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7991d 21h /i2c/trunk/rtl/verilog/i2c_master_top.v
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7996d 20h /i2c/trunk/rtl/verilog/i2c_master_top.v
13 Fixed some synthesis warnings. rherveille 8008d 00h /i2c/trunk/rtl/verilog/i2c_master_top.v
11 Changed RST_LVL define to parameter. rherveille 8016d 23h /i2c/trunk/rtl/verilog/i2c_master_top.v
10 Created new directory structure.
Added Verilog version.
rherveille 8038d 20h /i2c/trunk/rtl/verilog/i2c_master_top.v

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