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[/] [i2c/] [trunk/] [rtl/] [vhdl/] - Rev 35

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Rev Log message Author Age Path
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7747d 11h /i2c/trunk/rtl/vhdl/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7751d 09h /i2c/trunk/rtl/vhdl/
31 Core is now a Multimaster I2C controller. rherveille 7787d 19h /i2c/trunk/rtl/vhdl/
28 *** empty log message *** rherveille 7813d 13h /i2c/trunk/rtl/vhdl/
27 Cleaned up code rherveille 7813d 13h /i2c/trunk/rtl/vhdl/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7844d 17h /i2c/trunk/rtl/vhdl/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7982d 04h /i2c/trunk/rtl/vhdl/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8199d 01h /i2c/trunk/rtl/vhdl/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8203d 23h /i2c/trunk/rtl/vhdl/
10 Created new directory structure.
Added Verilog version.
rherveille 8245d 23h /i2c/trunk/rtl/vhdl/

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