URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [vhdl/] - Rev 39

Rev	Log message	Author	Age	Path
39	Forgot an 'end if' :-/	rherveille	7563d 08h	/i2c/trunk/rtl/vhdl/
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7566d 16h	/i2c/trunk/rtl/vhdl/
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7751d 22h	/i2c/trunk/rtl/vhdl/
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7755d 21h	/i2c/trunk/rtl/vhdl/
31	Core is now a Multimaster I2C controller.	rherveille	7792d 06h	/i2c/trunk/rtl/vhdl/
28	* empty log message *	rherveille	7818d 00h	/i2c/trunk/rtl/vhdl/
27	Cleaned up code	rherveille	7818d 00h	/i2c/trunk/rtl/vhdl/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7849d 04h	/i2c/trunk/rtl/vhdl/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7986d 15h	/i2c/trunk/rtl/vhdl/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8203d 12h	/i2c/trunk/rtl/vhdl/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8208d 11h	/i2c/trunk/rtl/vhdl/
10	Created new directory structure. Added Verilog version.	rherveille	8250d 10h	/i2c/trunk/rtl/vhdl/