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[/] [i2c/] [trunk/] [rtl/] [vhdl/] - Rev 51

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Rev Log message Author Age Path
51 Fixed simulation issue when writing to CR register rherveille 7286d 06h /i2c/trunk/rtl/vhdl/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7302d 09h /i2c/trunk/rtl/vhdl/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7311d 05h /i2c/trunk/rtl/vhdl/
39 Forgot an 'end if' :-/ rherveille 7501d 02h /i2c/trunk/rtl/vhdl/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7504d 10h /i2c/trunk/rtl/vhdl/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7689d 16h /i2c/trunk/rtl/vhdl/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7693d 15h /i2c/trunk/rtl/vhdl/
31 Core is now a Multimaster I2C controller. rherveille 7730d 00h /i2c/trunk/rtl/vhdl/
28 *** empty log message *** rherveille 7755d 18h /i2c/trunk/rtl/vhdl/
27 Cleaned up code rherveille 7755d 18h /i2c/trunk/rtl/vhdl/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7786d 22h /i2c/trunk/rtl/vhdl/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7924d 09h /i2c/trunk/rtl/vhdl/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 8141d 06h /i2c/trunk/rtl/vhdl/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 8146d 05h /i2c/trunk/rtl/vhdl/
10 Created new directory structure.
Added Verilog version.
rherveille 8188d 04h /i2c/trunk/rtl/vhdl/

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