OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [vhdl/] - Rev 74

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 5227d 13h /i2c/trunk/rtl/vhdl/
71 Fixed double wishbone write in a single access rherveille 5227d 13h /i2c/trunk/rtl/vhdl/
68 New directory structure. root 5536d 07h /i2c/trunk/rtl/vhdl/
67 Fixed slave_wait clocked event syntax rherveille 5569d 09h /i2c/trunk/rtl/vhdl/
66 Fixed type iscl_oen instead of scl_oen rherveille 5584d 09h /i2c/trunk/rtl/vhdl/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5584d 19h /i2c/trunk/rtl/vhdl/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5584d 19h /i2c/trunk/rtl/vhdl/
60 Added missing semicolons ';' on endif rherveille 6416d 17h /i2c/trunk/rtl/vhdl/
59 fixed short scl high pulse after clock stretch rherveille 6421d 19h /i2c/trunk/rtl/vhdl/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 7303d 18h /i2c/trunk/rtl/vhdl/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 7303d 18h /i2c/trunk/rtl/vhdl/
51 Fixed simulation issue when writing to CR register rherveille 7357d 19h /i2c/trunk/rtl/vhdl/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 7373d 22h /i2c/trunk/rtl/vhdl/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 7382d 18h /i2c/trunk/rtl/vhdl/
39 Forgot an 'end if' :-/ rherveille 7572d 15h /i2c/trunk/rtl/vhdl/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 7575d 22h /i2c/trunk/rtl/vhdl/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7761d 05h /i2c/trunk/rtl/vhdl/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7765d 03h /i2c/trunk/rtl/vhdl/
31 Core is now a Multimaster I2C controller. rherveille 7801d 13h /i2c/trunk/rtl/vhdl/
28 *** empty log message *** rherveille 7827d 07h /i2c/trunk/rtl/vhdl/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.