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[/] [i2c/] [trunk/] [rtl/] [vhdl/] - Rev 76

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 4453d 09h /i2c/trunk/rtl/vhdl/
75 Fixed sSDA generation rherveille 4459d 06h /i2c/trunk/rtl/vhdl/
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 4598d 03h /i2c/trunk/rtl/vhdl/
71 Fixed double wishbone write in a single access rherveille 4598d 03h /i2c/trunk/rtl/vhdl/
68 New directory structure. root 4906d 21h /i2c/trunk/rtl/vhdl/
67 Fixed slave_wait clocked event syntax rherveille 4939d 23h /i2c/trunk/rtl/vhdl/
66 Fixed type iscl_oen instead of scl_oen rherveille 4954d 23h /i2c/trunk/rtl/vhdl/
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4955d 09h /i2c/trunk/rtl/vhdl/
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4955d 09h /i2c/trunk/rtl/vhdl/
60 Added missing semicolons ';' on endif rherveille 5787d 07h /i2c/trunk/rtl/vhdl/
59 fixed short scl high pulse after clock stretch rherveille 5792d 08h /i2c/trunk/rtl/vhdl/
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6674d 07h /i2c/trunk/rtl/vhdl/
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6674d 08h /i2c/trunk/rtl/vhdl/
51 Fixed simulation issue when writing to CR register rherveille 6728d 09h /i2c/trunk/rtl/vhdl/
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 6744d 11h /i2c/trunk/rtl/vhdl/
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 6753d 07h /i2c/trunk/rtl/vhdl/
39 Forgot an 'end if' :-/ rherveille 6943d 04h /i2c/trunk/rtl/vhdl/
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 6946d 12h /i2c/trunk/rtl/vhdl/
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7131d 19h /i2c/trunk/rtl/vhdl/
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7135d 17h /i2c/trunk/rtl/vhdl/
31 Core is now a Multimaster I2C controller. rherveille 7172d 03h /i2c/trunk/rtl/vhdl/
28 *** empty log message *** rherveille 7197d 21h /i2c/trunk/rtl/vhdl/
27 Cleaned up code rherveille 7197d 21h /i2c/trunk/rtl/vhdl/
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7229d 01h /i2c/trunk/rtl/vhdl/
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7366d 12h /i2c/trunk/rtl/vhdl/
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7583d 08h /i2c/trunk/rtl/vhdl/
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7588d 07h /i2c/trunk/rtl/vhdl/
10 Created new directory structure.
Added Verilog version.
rherveille 7630d 07h /i2c/trunk/rtl/vhdl/

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