OpenCores
URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Rev 76

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 4127d 10h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
75 Fixed sSDA generation rherveille 4133d 07h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 4272d 04h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
68 New directory structure. root 4580d 22h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
67 Fixed slave_wait clocked event syntax rherveille 4614d 00h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
66 Fixed type iscl_oen instead of scl_oen rherveille 4628d 23h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4629d 09h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
60 Added missing semicolons ';' on endif rherveille 5461d 08h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
59 fixed short scl high pulse after clock stretch rherveille 5466d 09h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6348d 08h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6348d 09h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 6418d 12h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
39 Forgot an 'end if' :-/ rherveille 6617d 05h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 6620d 13h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 6805d 20h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 6809d 18h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
31 Core is now a Multimaster I2C controller. rherveille 6846d 04h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
27 Cleaned up code rherveille 6871d 22h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
24 Fixed some reported minor start/stop generation timing issuess. rherveille 6903d 02h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7040d 12h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.