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[/] [i2c/] [trunk/] [rtl/] [vhdl/] [i2c_master_bit_ctrl.vhd] - Rev 72

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Rev Log message Author Age Path
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 4215d 10h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
68 New directory structure. root 4524d 04h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
67 Fixed slave_wait clocked event syntax rherveille 4557d 06h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
66 Fixed type iscl_oen instead of scl_oen rherveille 4572d 06h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4572d 16h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
60 Added missing semicolons ';' on endif rherveille 5404d 15h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
59 fixed short scl high pulse after clock stretch rherveille 5409d 16h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6291d 15h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6291d 16h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 6361d 19h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
39 Forgot an 'end if' :-/ rherveille 6560d 12h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.
rherveille 6563d 20h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 6749d 03h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 6753d 01h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
31 Core is now a Multimaster I2C controller. rherveille 6789d 11h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
27 Cleaned up code rherveille 6815d 04h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
24 Fixed some reported minor start/stop generation timing issuess. rherveille 6846d 09h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 6983d 19h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7205d 15h /i2c/trunk/rtl/vhdl/i2c_master_bit_ctrl.vhd

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