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[/] [i2c/] [trunk] - Rev 46

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Rev Log message Author Age Path
46 Fixed slave address MSB='1' bug rherveille 7469d 04h /i2c/trunk
45 Added slave address configurability rherveille 7469d 04h /i2c/trunk
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 7554d 07h /i2c/trunk
40 Fix a blocking vs. non-blocking error in the wb_dat output mux. rherveille 7564d 05h /i2c/trunk
39 Forgot an 'end if' :-/ rherveille 7584d 01h /i2c/trunk
38 Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line.
Fixed a potential bug in the byte controller's host-acknowledge generation.		 rherveille 7587d 08h /i2c/trunk
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7624d 00h /i2c/trunk
36 Fixed cmd_ack generation item (no bug). rherveille 7739d 01h /i2c/trunk
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7772d 15h /i2c/trunk
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7776d 13h /i2c/trunk
33 Fixed a bug in the Command Register declaration. rherveille 7798d 23h /i2c/trunk
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7808d 22h /i2c/trunk
31 Core is now a Multimaster I2C controller. rherveille 7812d 23h /i2c/trunk
30 Small code simplifications rherveille 7812d 23h /i2c/trunk
29 Core is now a Multimaster I2C controller rherveille 7813d 00h /i2c/trunk
28 *** empty log message *** rherveille 7838d 17h /i2c/trunk
27 Cleaned up code rherveille 7838d 17h /i2c/trunk
26 *** empty log message *** rherveille 7842d 01h /i2c/trunk
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7869d 21h /i2c/trunk
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7869d 21h /i2c/trunk

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