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Subversion Repositories i2c

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 5125d 12h /
75 Fixed sSDA generation rherveille 5131d 09h /
74 Added SCL/SDA line filter rherveille 5270d 05h /
73 Fixed double wishbone write in a single access rherveille 5270d 05h /
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 5270d 05h /
71 Fixed double wishbone write in a single access rherveille 5270d 05h /
70 Added old uploaded documents to new repository. root 5578d 08h /
69 Added old uploaded documents to new repository. root 5578d 23h /
68 New directory structure. root 5578d 23h /
67 Fixed slave_wait clocked event syntax rherveille 5612d 01h /
66 Fixed type iscl_oen instead of scl_oen rherveille 5627d 01h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5627d 11h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5627d 11h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5627d 11h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5628d 01h /
61 Removed synopsys link; it's not used rherveille 6282d 13h /
60 Added missing semicolons ';' on endif rherveille 6459d 09h /
59 fixed short scl high pulse after clock stretch rherveille 6464d 11h /
58 fixed (n)ack generation rherveille 6496d 12h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 6496d 13h /

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