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Rev Log message Author Age Path
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 8214d 01h /
13 Fixed some synthesis warnings. rherveille 8225d 05h /
12 no message rherveille 8230d 20h /
11 Changed RST_LVL define to parameter. rherveille 8234d 04h /
10 Created new directory structure.
Added Verilog version.
rherveille 8256d 00h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 8325d 19h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 8325d 19h /
7 added some remarks, fixed some sensitivity lists rherveille 8394d 22h /
6 fixed typo txt -> txr rherveille 8399d 02h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 8406d 00h /
4 WISHBONE I2C Master Core: initial release rherveille 8458d 03h /
3 This commit was manufactured by cvs2svn to create tag 'first'. 8520d 02h /
2 initial release rherveille 8520d 02h /
1 Standard project directories initialized by cvs2svn. 8520d 02h /

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