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Rev Log message Author Age Path
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7137d 17h /
23 *** empty log message *** rherveille 7264d 22h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7275d 04h /
21 no message rherveille 7361d 04h /
20 Added Appendix A rherveille 7361d 04h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 7365d 01h /
18 no message rherveille 7391d 21h /
17 C-include file.
Initial release
rherveille 7480d 01h /
16 Changed PRER reset value from 0x0000 to 0xffff, conform specs. rherveille 7492d 00h /
15 Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version.
Code updated, is now up-to-date to doc. rev.0.4.
Added headers.
rherveille 7496d 23h /
14 Fixed wb_ack_o generation bug.
Fixed bug in the byte_controller statemachine.
Added headers.
rherveille 7496d 23h /
13 Fixed some synthesis warnings. rherveille 7508d 03h /
12 no message rherveille 7513d 19h /
11 Changed RST_LVL define to parameter. rherveille 7517d 02h /
10 Created new directory structure.
Added Verilog version.
rherveille 7538d 23h /
9 Created directory structure (documentation, vhdl, verilog) rherveille 7608d 18h /
8 Created directory structure (documentation, vhdl, verilog) rherveille 7608d 18h /
7 added some remarks, fixed some sensitivity lists rherveille 7677d 21h /
6 fixed typo txt -> txr rherveille 7682d 00h /
5 fixed an incomplete sensitivity list on assign_dato process rherveille 7688d 23h /

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