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Rev Log message Author Age Path
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.
rherveille 7398d 05h /
36 Fixed cmd_ack generation item (no bug). rherveille 7513d 06h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7546d 20h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7550d 18h /
33 Fixed a bug in the Command Register declaration. rherveille 7573d 04h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.
rherveille 7583d 03h /
31 Core is now a Multimaster I2C controller. rherveille 7587d 04h /
30 Small code simplifications rherveille 7587d 04h /
29 Core is now a Multimaster I2C controller rherveille 7587d 05h /
28 *** empty log message *** rherveille 7612d 22h /
27 Cleaned up code rherveille 7612d 22h /
26 *** empty log message *** rherveille 7616d 06h /
25 Added timing tests to i2c_model.
Updated testbench.
rherveille 7644d 02h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7644d 02h /
23 *** empty log message *** rherveille 7771d 08h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 7781d 13h /
21 no message rherveille 7867d 13h /
20 Added Appendix A rherveille 7867d 13h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.
rherveille 7871d 10h /
18 no message rherveille 7898d 06h /

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