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Rev Log message Author Age Path
37 Fixed a type in example 1
Changed 'RW' to 'W' in command register description.
Changed 'RW' to 'W' in transmit register description.		 rherveille 7625d 22h /
36 Fixed cmd_ack generation item (no bug). rherveille 7740d 23h /
35 Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles. rherveille 7774d 13h /
34 Fixed a few 'arbitration lost' bugs. VHDL version only. rherveille 7778d 11h /
33 Fixed a bug in the Command Register declaration. rherveille 7800d 21h /
32 Multi-master capabilities added to the core. Changed documentation accordingly.
Updated some timing diagrams.		 rherveille 7810d 20h /
31 Core is now a Multimaster I2C controller. rherveille 7814d 21h /
30 Small code simplifications rherveille 7814d 21h /
29 Core is now a Multimaster I2C controller rherveille 7814d 22h /
28 *** empty log message *** rherveille 7840d 15h /
27 Cleaned up code rherveille 7840d 15h /
26 *** empty log message *** rherveille 7843d 23h /
25 Added timing tests to i2c_model.
Updated testbench.		 rherveille 7871d 19h /
24 Fixed some reported minor start/stop generation timing issuess. rherveille 7871d 19h /
23 *** empty log message *** rherveille 7999d 00h /
22 Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment. rherveille 8009d 06h /
21 no message rherveille 8095d 06h /
20 Added Appendix A rherveille 8095d 06h /
19 Fixed some race conditions in the i2c-slave model.
Added debug information.
Added headers.		 rherveille 8099d 03h /
18 no message rherveille 8125d 23h /

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