URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

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Rev	Log message	Author	Age	Path
40	Fix a blocking vs. non-blocking error in the wb_dat output mux.	rherveille	7549d 06h	/
39	Forgot an 'end if' :-/	rherveille	7569d 02h	/
38	Fixed a bug in the Arbitration Lost generation caused by delay on the (external) sda line. Fixed a potential bug in the byte controller's host-acknowledge generation.	rherveille	7572d 10h	/
37	Fixed a type in example 1 Changed 'RW' to 'W' in command register description. Changed 'RW' to 'W' in transmit register description.	rherveille	7609d 02h	/
36	Fixed cmd_ack generation item (no bug).	rherveille	7724d 03h	/
35	Fixed a bug where the core would trigger an erroneous 'arbitration lost' interrupt after being reset, when the reset pulse width < 3 clk cycles.	rherveille	7757d 17h	/
34	Fixed a few 'arbitration lost' bugs. VHDL version only.	rherveille	7761d 15h	/
33	Fixed a bug in the Command Register declaration.	rherveille	7784d 00h	/
32	Multi-master capabilities added to the core. Changed documentation accordingly. Updated some timing diagrams.	rherveille	7794d 00h	/
31	Core is now a Multimaster I2C controller.	rherveille	7798d 01h	/
30	Small code simplifications	rherveille	7798d 01h	/
29	Core is now a Multimaster I2C controller	rherveille	7798d 02h	/
28	* empty log message *	rherveille	7823d 19h	/
27	Cleaned up code	rherveille	7823d 19h	/
26	* empty log message *	rherveille	7827d 03h	/
25	Added timing tests to i2c_model. Updated testbench.	rherveille	7854d 23h	/
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7854d 23h	/
23	* empty log message *	rherveille	7982d 04h	/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	7992d 09h	/
21	no message	rherveille	8078d 10h	/

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Subversion Repositories i2c

[/] - Rev 40

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