URL https://opencores.org/ocsvn/i2c/i2c/trunk

Subversion Repositories i2c

[/] - Rev 44

Rev	Log message	Author	Age	Path
24	Fixed some reported minor start/stop generation timing issuess.	rherveille	7878d 22h	/
23	* empty log message *	rherveille	8006d 03h	/
22	Fixed a small timing bug in the bit controller.\nAdded verilog simulation environment.	rherveille	8016d 08h	/
21	no message	rherveille	8102d 09h	/
20	Added Appendix A	rherveille	8102d 09h	/
19	Fixed some race conditions in the i2c-slave model. Added debug information. Added headers.	rherveille	8106d 06h	/
18	no message	rherveille	8133d 01h	/
17	C-include file. Initial release	rherveille	8221d 06h	/
16	Changed PRER reset value from 0x0000 to 0xffff, conform specs.	rherveille	8233d 05h	/
15	Split i2c_master_core.vhd into separate files for each entity; same layout as verilog version. Code updated, is now up-to-date to doc. rev.0.4. Added headers.	rherveille	8238d 04h	/