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Rev Log message Author Age Path
61 Removed synopsys link; it's not used rherveille 4703d 13h /
60 Added missing semicolons ';' on endif rherveille 4880d 10h /
59 fixed short scl high pulse after clock stretch rherveille 4885d 11h /
58 fixed (n)ack generation rherveille 4917d 13h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 4917d 13h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 5470d 10h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 5471d 12h /
54 Fixed scl, sda delay. rherveille 5471d 12h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 5767d 10h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 5767d 11h /
51 Fixed simulation issue when writing to CR register rherveille 5821d 11h /
50 *** empty log message *** rherveille 5836d 06h /
49 Added testbench rherveille 5836d 06h /
48 Fixed a bug in the arbitration-lost signal generation. VHDL version only. rherveille 5837d 14h /
47 Fixed a potential bug in the statemachine. During a 'stop' 2 cmd_ack signals were generated. Possibly canceling a new start command. rherveille 5846d 10h /
46 Fixed slave address MSB='1' bug rherveille 5921d 11h /
45 Added slave address configurability rherveille 5921d 11h /
44 This commit was manufactured by cvs2svn to create tag 'rel_1'. 6006d 13h /
43 Fixed a bug in the timing section. Changed 'tst_scl' into 'tst_sto'. rherveille 6006d 13h /
42 This commit was manufactured by cvs2svn to create tag 'asyst_3'. 6016d 11h /

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