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Rev Log message Author Age Path
68 New directory structure. root 5079d 05h /
67 Fixed slave_wait clocked event syntax rherveille 5112d 07h /
66 Fixed type iscl_oen instead of scl_oen rherveille 5127d 06h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 5127d 16h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 5127d 16h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 5127d 17h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 5128d 07h /
61 Removed synopsys link; it's not used rherveille 5782d 18h /
60 Added missing semicolons ';' on endif rherveille 5959d 15h /
59 fixed short scl high pulse after clock stretch rherveille 5964d 16h /
58 fixed (n)ack generation rherveille 5996d 18h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5996d 18h /
56 Fixed Tsu:sta timing check.
Added Thd:sta timing check.
rherveille 6549d 15h /
55 Fixed register overwrite issue.
Removed full_case pragma, replaced it by a default statement.
rherveille 6550d 18h /
54 Fixed scl, sda delay. rherveille 6550d 18h /
53 Fixed previous fix :) Made a variable vs signal mistake. rherveille 6846d 15h /
52 Fixed a bug where the core would signal an arbitration lost (AL bit set), when another master controls the bus and the other master generates a STOP bit. rherveille 6846d 16h /
51 Fixed simulation issue when writing to CR register rherveille 6900d 17h /
50 *** empty log message *** rherveille 6915d 11h /
49 Added testbench rherveille 6915d 11h /

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