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Subversion Repositories i2c

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Rev Log message Author Age Path
76 Updated filter_cnt generation rherveille 3646d 05h /
75 Fixed sSDA generation rherveille 3652d 02h /
74 Added SCL/SDA line filter rherveille 3790d 22h /
73 Fixed double wishbone write in a single access rherveille 3790d 22h /
72 Fixed AL generation
Added median filter on SDA and SCL inputs
rherveille 3790d 22h /
71 Fixed double wishbone write in a single access rherveille 3790d 23h /
70 Added old uploaded documents to new repository. root 4099d 01h /
69 Added old uploaded documents to new repository. root 4099d 16h /
68 New directory structure. root 4099d 16h /
67 Fixed slave_wait clocked event syntax rherveille 4132d 19h /
66 Fixed type iscl_oen instead of scl_oen rherveille 4147d 18h /
65 Changed wb_adr_i from unsigned to std_logic_vector rherveille 4148d 04h /
64 Added SCL clock synchronization logic
Fixed slave_wait signal generation
rherveille 4148d 04h /
63 Added clock synchronization logic
Fixed slave_wait signal
rherveille 4148d 05h /
62 Fixed synopsys miss spell (synopsis)
Fixed cr[0] register width
Fixed ! usage instead of ~
Fixed bit controller parameter width to 18bits
rherveille 4148d 18h /
61 Removed synopsys link; it's not used rherveille 4803d 06h /
60 Added missing semicolons ';' on endif rherveille 4980d 03h /
59 fixed short scl high pulse after clock stretch rherveille 4985d 04h /
58 fixed (n)ack generation rherveille 5017d 06h /
57 fixed short scl high pulse after clock stretch
fixed slave model not returning correct '(n)ack' signal
rherveille 5017d 06h /

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