URL https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk

Subversion Repositories iso7816_3_master

[/] [iso7816_3_master/] [trunk/] [test/] [iso7816_3_t0_analyzer.v] - Rev 17

Rev	Log message	Author	Age	Path
17	yet another fix of the analyzer: ATR, and convention handling	acapola	4840d 03h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
15	tpdu level tasks inverse convention	acapola	4845d 02h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
13	Corrections in analyzer to handle TDi and historical bytes in ATR and PPS todo: handle inverse convention	acapola	4849d 05h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
12	pps sequence added to test bench endOfTx added to TxCore	acapola	4860d 01h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
11	added BSD licence header to files	acapola	4860d 05h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
10	communication direction probe added	acapola	4860d 07h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
8		acapola	4868d 01h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
7	- rx/tx use "cyclesPerEtu" input - "stopBit" status bit timing fixed - analyzer: "lastByte" and "bytesCnt" functional	acapola	4869d 01h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
6	analyzer added to test bench, not functional yet...	acapola	4870d 01h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
5	draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself)	acapola	4871d 01h	/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v