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[/] [iso7816_3_master/] [trunk/] [test/] [iso7816_3_t0_analyzer.v] - Rev 20

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20 acapola 4771d 10h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
19 ATR analyzer fixed to handle 3b 90 97 40 20 correctly acapola 4771d 23h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
18 A bunch of synthesis error/warning removed.
Master and analyzer synthesis OK on Spartan6 FPGA		 acapola 4813d 07h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
17 yet another fix of the analyzer: ATR, and convention handling acapola 4830d 06h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
15 tpdu level tasks
inverse convention		 acapola 4835d 05h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
13 Corrections in analyzer to handle TDi and historical bytes in ATR and PPS
todo: handle inverse convention		 acapola 4839d 08h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
12 pps sequence added to test bench
endOfTx added to TxCore		 acapola 4850d 04h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
11 added BSD licence header to files acapola 4850d 08h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
10 communication direction probe added acapola 4850d 10h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
8 acapola 4858d 05h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
7 - rx/tx use "cyclesPerEtu" input
- "stopBit" status bit timing fixed
- analyzer: "lastByte" and "bytesCnt" functional		 acapola 4859d 04h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
6 analyzer added to test bench, not functional yet... acapola 4860d 04h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v
5 draft of t=0 protocol analyzer (to ease debuging, and eventually as an ip itself) acapola 4861d 05h /iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v

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