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[/] [iso7816_3_master/] [trunk/] [test/] [tbIso7816_3_Master.v] - Rev 20

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20 acapola 4771d 09h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
19 ATR analyzer fixed to handle 3b 90 97 40 20 correctly acapola 4771d 23h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
18 A bunch of synthesis error/warning removed.
Master and analyzer synthesis OK on Spartan6 FPGA		 acapola 4813d 07h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
15 tpdu level tasks
inverse convention		 acapola 4835d 05h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
14 Task to send strings as bytes improved acapola 4838d 04h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
13 Corrections in analyzer to handle TDi and historical bytes in ATR and PPS
todo: handle inverse convention		 acapola 4839d 08h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
12 pps sequence added to test bench
endOfTx added to TxCore		 acapola 4850d 04h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
11 added BSD licence header to files acapola 4850d 08h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
10 communication direction probe added acapola 4850d 09h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
9 parity convention fixed acapola 4856d 06h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
8 acapola 4858d 04h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
7 - rx/tx use "cyclesPerEtu" input
- "stopBit" status bit timing fixed
- analyzer: "lastByte" and "bytesCnt" functional		 acapola 4859d 04h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
6 analyzer added to test bench, not functional yet... acapola 4860d 04h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
4 Basic test bench completed for T=0: a card send ATR, reader send a command
TODO: add cycles/ETU management (start at 372, then adjust in case of PPS...)		 acapola 4862d 05h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v
3 initial draft, not functional yet acapola 4869d 06h /iso7816_3_master/trunk/test/tbIso7816_3_Master.v

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