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26 Changed the VHDL simulation logging code to match the SW simulator.
The JBC ACC.x instruction is a special case that needs a tiny hack...
Note this affects only the simulation test bench, not the RTL!		 ja_rd 3818d 22h /
25 Pre-generated object code packages updated with new test bench. ja_rd 3818d 22h /
24 Basic CPU test bench modified to catch previously undetected bug in CLR BIT. Still too weak though... ja_rd 3818d 22h /
23 Fixed CLR.bit when ACC was the target.
Implemented solution suggested by Stephane Bouyat, worked like a charm!		 ja_rd 3818d 22h /
22 Fixed comments in object code package generation script.
The comments were awfully wrong -- leftover from another project, actually.		 ja_rd 4110d 01h /
21 ja_rd 4125d 06h /
20 ja_rd 4125d 06h /
19 Refactor: interrupts made 100% compatible to original:
IRQ priority logic implemented as in original MCS51.
Register IP implemented.
Interrupt mini-testbench code updated accordingly.		 ja_rd 4125d 06h /
18 Refactor: interrupts made 100% compatible to original:
IRQ priority logic implemented as in original MCS51.
Register IP implemented.
Interrupt mini-testbench code updated accordingly.		 ja_rd 4125d 06h /
17 Refactor: interrupts made 100% compatible to original:
IRQ priority logic implemented as in original MCS51.
Register IP implemented.
Interrupt mini-testbench code updated accordingly.		 ja_rd 4125d 06h /
16 Test bench modified: now tests IRAM and SFR addresses when testing direct mode instructions (instead of only IRAM). ja_rd 4127d 03h /
15 Test bench modified: now tests IRAM and SFR addresses when testing direct mode instructions (instead of only IRAM). ja_rd 4131d 00h /
14 BUG FIX: <DJNZ dir, rel> didn't work when addressing an SFR.
Signal direct_addressing fixed.		 ja_rd 4131d 05h /
13 BUG FIX: <DJNZ dir, rel> was tested only with IRAM addresses.
Now it's tested with an SFR too.
The test package has been fixed too with a XRAM configuration suitable for the test bench (it was zero).		 ja_rd 4131d 06h /
12 BUG FIX: The build script did not configure XDATA space properly.
XDATA size was zero, which made the HW tests fail.		 ja_rd 4131d 09h /
11 Removed old 'demos' directory. These files are now in the 'boards' directory. ja_rd 4193d 08h /
10 Updated 'quickstart' to reflect new organization of demo directory. ja_rd 4193d 08h /
9 Fixed quartus-2 project file -- replaced absolute output path with relative path. ja_rd 4193d 09h /
8 Added support to build demos on another board: Avnet's Spartan-3A Evaluation Board. ja_rd 4196d 00h /
7 Removed obsolete comment from core include file. ja_rd 4196d 01h /
6 Added a 'LED blinker' program to try the core on boards with no RS232 connector. ja_rd 4196d 01h /
5 Committed source and project files for Dhrystone demo on Terasic's DE-1 board. ja_rd 4197d 10h /
4 Committed support tools including simulator. ja_rd 4197d 11h /
3 Committed documentation and example programs. ja_rd 4197d 12h /
2 Full VHDL sources and Modelsim scripts.
This is a migration of an existing project.		 ja_rd 4197d 12h /
1 The project and the structure was created root 4197d 12h /

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