URL https://opencores.org/ocsvn/light52/light52/trunk

Subversion Repositories light52

[/] [light52/] [trunk/] [vhdl/] - Rev 26

Rev	Log message	Author	Age	Path
26	Changed the VHDL simulation logging code to match the SW simulator. The JBC ACC.x instruction is a special case that needs a tiny hack... Note this affects only the simulation test bench, not the RTL!	ja_rd	3815d 04h	/light52/trunk/vhdl/
23	Fixed CLR.bit when ACC was the target. Implemented solution suggested by Stephane Bouyat, worked like a charm!	ja_rd	3815d 04h	/light52/trunk/vhdl/
17	Refactor: interrupts made 100% compatible to original: IRQ priority logic implemented as in original MCS51. Register IP implemented. Interrupt mini-testbench code updated accordingly.	ja_rd	4121d 12h	/light52/trunk/vhdl/
14	BUG FIX: <DJNZ dir, rel> didn't work when addressing an SFR. Signal direct_addressing fixed.	ja_rd	4127d 11h	/light52/trunk/vhdl/
11	Removed old 'demos' directory. These files are now in the 'boards' directory.	ja_rd	4189d 14h	/light52/trunk/vhdl/
2	Full VHDL sources and Modelsim scripts. This is a migration of an existing project.	ja_rd	4193d 18h	/light52/trunk/vhdl/