URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] - Rev 20

Rev	Log message	Author	Age	Path
20	VHDL template for test benches	ja_rd	5548d 21h	/
19	Fixed a bug (intr pulses longer than 1 clock cycle failed in some circumstances) Added an output to the core to mark the fetch cycle of all instructions Started to add timing diagrams	ja_rd	5548d 21h	/
18	Uncluttered the signal display a bit	ja_rd	5548d 21h	/
17	Comments added	ja_rd	5635d 00h	/
16	adding LST filed generated by TASM	ja_rd	5635d 00h	/
15	Names and contents of some files changed	ja_rd	5635d 00h	/
14	Syntax changed from CP/M ASM to DOS TASM Success code changed	ja_rd	5635d 00h	/
13	Minor changes in embedded code changed (success code now stands out better visually) Comments added explaining the TB mechanincs	ja_rd	5635d 00h	/
12	Minor changes in embedded code changed (success code now stands out better visually)	ja_rd	5635d 00h	/
11	typos fixed	ja_rd	5635d 00h	/
10	minor edits, comments clarified	ja_rd	5662d 14h	/
9	Design notes now done with LaTeX, OpenOffice source removed	ja_rd	5667d 21h	/
8	LaTeX source for the design notes	ja_rd	5667d 21h	/
7	Minor edits and clarifications, plus document is now generated with LaTeX instead of OpenOffice	ja_rd	5667d 21h	/
6	microcode bug in INR M, #setacy flag missing	ja_rd	5732d 00h	/
5	microcode bug in INR M, #setacy flag missing	ja_rd	5732d 00h	/
4	light8080.vhdl comments in header corrected (they were obsolete)	ja_rd	6011d 03h	/
3	added author line and license file	ja_rd	6017d 18h	/
2	initial commit	ja_rd	6019d 04h	/
1	Standard project directories initialized by cvs2svn.		6019d 04h	/