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22 Totally changed -- vhdl code generated from a template
Interrupts tested from software using a simulated interrupt controller
ja_rd 5574d 02h /
21 Totally changed -- vhdl code generated from a template ja_rd 5574d 02h /
20 VHDL template for test benches ja_rd 5574d 03h /
19 Fixed a bug (intr pulses longer than 1 clock cycle failed in some circumstances)
Added an output to the core to mark the fetch cycle of all instructions
Started to add timing diagrams
ja_rd 5574d 03h /
18 Uncluttered the signal display a bit ja_rd 5574d 03h /
17 Comments added ja_rd 5660d 05h /
16 adding LST filed generated by TASM ja_rd 5660d 06h /
15 Names and contents of some files changed ja_rd 5660d 06h /
14 Syntax changed from CP/M ASM to DOS TASM
Success code changed
ja_rd 5660d 06h /
13 Minor changes in embedded code changed (success code now stands out better visually)
Comments added explaining the TB mechanincs
ja_rd 5660d 06h /
12 Minor changes in embedded code changed (success code now stands out better visually) ja_rd 5660d 06h /
11 typos fixed ja_rd 5660d 06h /
10 minor edits, comments clarified ja_rd 5687d 20h /
9 Design notes now done with LaTeX, OpenOffice source removed ja_rd 5693d 03h /
8 LaTeX source for the design notes ja_rd 5693d 03h /
7 Minor edits and clarifications,
plus document is now generated with LaTeX instead of OpenOffice
ja_rd 5693d 03h /
6 microcode bug in INR M, #setacy flag missing ja_rd 5757d 06h /
5 microcode bug in INR M, #setacy flag missing ja_rd 5757d 06h /
4 light8080.vhdl

comments in header corrected (they were obsolete)
ja_rd 6036d 08h /
3 added author line and license file ja_rd 6042d 23h /

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