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Rev	Log message	Author	Age	Path
73	New tool for VHDL object code constant generation. Old VHDL template tool moved to tools directory.	ja_rd	4433d 22h	/
72	Added specs document for VHDL/Verilog CPU core	ja_rd	4433d 22h	/
71	IMSAI manual removed, no longer used	ja_rd	4433d 22h	/
70	Added new VHDL SoC for demonstration purposes	ja_rd	4433d 22h	/
69	New simulation scripts for Modelsim in new separate directory. Includes old test benches for CPU VHDL core and new test benches for SoC VHDL core	ja_rd	4433d 22h	/
68	Corrected ihex2vlog tool to enable explicit RAM declaration for Spartan 2.	motilito	4444d 18h	/
67	Corrected bugs in the Small-C compiler.	motilito	4445d 20h	/
66	Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code.	motilito	4460d 18h	/
65	Adding Verilog initial version to the svn. Added the c80 Small-C compiler and AS80 assembler.	motilito	4472d 01h	/
64	BUG FIX: Flags CY and AC were not clear by logic instructions Added new flag to microcode: clr_acy Used new flag to clear AC and CY flags unconditonally Modified microcode for XR, OR and AN* to use new flag Modified microcode assembler to support new flag Addex explaination of new flag to documentation Old fix that worked only for XR* instructions removed Test bench tb0 modified to test CY clearance minimally (AC untested!) Pre-generated vhel test bench tb0 altered accordingly	ja_rd	4481d 02h	/
63	Modified syntax of ARGV parameter for compatibility to later versions of Perl	ja_rd	4481d 02h	/
62	Changed all hard tabs to spaces as preamble to a minor refactor	ja_rd	4481d 11h	/
61	Basic demo updated: main entity name changed to keep synthesis too happy	ja_rd	4849d 12h	/
60	Fixed nasty typo in pin constraints file (clock input)	ja_rd	4853d 18h	/
59	tabs to spaces	ja_rd	4878d 01h	/
58	tabs to spaces	ja_rd	4878d 01h	/
57	removed unfinished CPM demo files	ja_rd	5062d 15h	/
56	file list updated	ja_rd	5062d 15h	/
55	Altair 4K Basic demo on DE-1 board	ja_rd	5062d 15h	/
54	BUG FIX: XOR operations wre not clearing CY and ACY	ja_rd	5062d 15h	/
53	added interrupt for single-stepping cleaned up comments a bit	ja_rd	5418d 15h	/
52	test bench compilation script sanitized a little	ja_rd	5418d 15h	/
51	interrupt test bench adapted to the fix in IE instruction	ja_rd	5418d 15h	/
50	interrupt test bench adapted to the fix in IE instruction	ja_rd	5418d 15h	/
49	fixed: IE now enables interrupts after a 1-instruction delay (it was enabling interrupts immediately)	ja_rd	5418d 15h	/
48	clarification of some terms in the comments	ja_rd	5419d 07h	/
47	edited the file list and added a few remarks	ja_rd	5419d 07h	/
46	minor change in signal color for better readability	ja_rd	5419d 08h	/
45	Added modelsim scripts for the test benches	ja_rd	5419d 08h	/
44	fixed error in RST test, added support for long intr tests added a test of a 'long' intr pulse	ja_rd	5419d 08h	/

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