Subversion Repositories light8080

[/] - Rev 75


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
75 Updated file list ja_rd 4354d 15h /
74 Testbenches for VHDL core moved to sw/tb.
Added a mini-demo for the VHDL SoC on the DE-1 dev board.
Added a mini-testbench for the VHDL SoC.
ja_rd 4354d 15h /
73 New tool for VHDL object code constant generation.
Old VHDL template tool moved to tools directory.
ja_rd 4354d 15h /
72 Added specs document for VHDL/Verilog CPU core ja_rd 4354d 15h /
71 IMSAI manual removed, no longer used ja_rd 4354d 15h /
70 Added new VHDL SoC for demonstration purposes ja_rd 4354d 15h /
69 New simulation scripts for Modelsim in new separate directory.
Includes old test benches for CPU VHDL core and new test benches for SoC VHDL core
ja_rd 4354d 15h /
68 Corrected ihex2vlog tool to enable explicit RAM declaration for Spartan 2. motilito 4365d 11h /
67 Corrected bugs in the Small-C compiler. motilito 4366d 13h /
66 Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code. motilito 4381d 11h /
65 Adding Verilog initial version to the svn.
Added the c80 Small-C compiler and AS80 assembler.
motilito 4392d 19h /
64 BUG FIX: Flags CY and AC were not clear by logic instructions
Added new flag to microcode: clr_acy
Used new flag to clear AC and CY flags unconditonally
Modified microcode for XR*, OR* and AN* to use new flag
Modified microcode assembler to support new flag
Addex explaination of new flag to documentation
Old fix that worked only for XR* instructions removed
Test bench tb0 modified to test CY clearance minimally (AC untested!)
Pre-generated vhel test bench tb0 altered accordingly
ja_rd 4401d 19h /
63 Modified syntax of ARGV parameter for compatibility to later versions of Perl ja_rd 4401d 19h /
62 Changed all hard tabs to spaces as preamble to a minor refactor ja_rd 4402d 05h /
61 Basic demo updated: main entity name changed to keep synthesis too happy ja_rd 4770d 06h /
60 Fixed nasty typo in pin constraints file (clock input) ja_rd 4774d 11h /
59 tabs to spaces ja_rd 4798d 19h /
58 tabs to spaces ja_rd 4798d 19h /
57 removed unfinished CPM demo files ja_rd 4983d 08h /
56 file list updated ja_rd 4983d 08h /

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.