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Rev Log message Author Age Path
64 BUG FIX: Flags CY and AC were not clear by logic instructions
Added new flag to microcode: clr_acy
Used new flag to clear AC and CY flags unconditonally
Modified microcode for XR*, OR* and AN* to use new flag
Modified microcode assembler to support new flag
Addex explaination of new flag to documentation
Old fix that worked only for XR* instructions removed
Test bench tb0 modified to test CY clearance minimally (AC untested!)
Pre-generated vhel test bench tb0 altered accordingly
ja_rd 4492d 13h /
63 Modified syntax of ARGV parameter for compatibility to later versions of Perl ja_rd 4492d 13h /
62 Changed all hard tabs to spaces as preamble to a minor refactor ja_rd 4492d 23h /
61 Basic demo updated: main entity name changed to keep synthesis too happy ja_rd 4861d 00h /
60 Fixed nasty typo in pin constraints file (clock input) ja_rd 4865d 05h /
59 tabs to spaces ja_rd 4889d 13h /
58 tabs to spaces ja_rd 4889d 13h /
57 removed unfinished CPM demo files ja_rd 5074d 03h /
56 file list updated ja_rd 5074d 03h /
55 Altair 4K Basic demo on DE-1 board ja_rd 5074d 03h /

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