OpenCores
URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] - Rev 71

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
71 IMSAI manual removed, no longer used ja_rd 4431d 08h /light8080/
70 Added new VHDL SoC for demonstration purposes ja_rd 4431d 08h /light8080/
69 New simulation scripts for Modelsim in new separate directory.
Includes old test benches for CPU VHDL core and new test benches for SoC VHDL core		 ja_rd 4431d 08h /light8080/
68 Corrected ihex2vlog tool to enable explicit RAM declaration for Spartan 2. motilito 4442d 04h /light8080/
67 Corrected bugs in the Small-C compiler. motilito 4443d 06h /light8080/
66 Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code. motilito 4458d 04h /light8080/
65 Adding Verilog initial version to the svn.
Added the c80 Small-C compiler and AS80 assembler.		 motilito 4469d 12h /light8080/
64 BUG FIX: Flags CY and AC were not clear by logic instructions
Added new flag to microcode: clr_acy
Used new flag to clear AC and CY flags unconditonally
Modified microcode for XR*, OR* and AN* to use new flag
Modified microcode assembler to support new flag
Addex explaination of new flag to documentation
Old fix that worked only for XR* instructions removed
Test bench tb0 modified to test CY clearance minimally (AC untested!)
Pre-generated vhel test bench tb0 altered accordingly		 ja_rd 4478d 12h /light8080/
63 Modified syntax of ARGV parameter for compatibility to later versions of Perl ja_rd 4478d 12h /light8080/
62 Changed all hard tabs to spaces as preamble to a minor refactor ja_rd 4478d 21h /light8080/
61 Basic demo updated: main entity name changed to keep synthesis too happy ja_rd 4846d 23h /light8080/
60 Fixed nasty typo in pin constraints file (clock input) ja_rd 4851d 04h /light8080/
59 tabs to spaces ja_rd 4875d 11h /light8080/
58 tabs to spaces ja_rd 4875d 11h /light8080/
57 removed unfinished CPM demo files ja_rd 5060d 01h /light8080/
56 file list updated ja_rd 5060d 01h /light8080/
55 Altair 4K Basic demo on DE-1 board ja_rd 5060d 01h /light8080/
54 BUG FIX: XOR operations wre not clearing CY and ACY ja_rd 5060d 01h /light8080/
53 added interrupt for single-stepping
cleaned up comments a bit		 ja_rd 5416d 02h /light8080/
52 test bench compilation script sanitized a little ja_rd 5416d 02h /light8080/
51 interrupt test bench adapted to the fix in IE instruction ja_rd 5416d 02h /light8080/
50 interrupt test bench adapted to the fix in IE instruction ja_rd 5416d 02h /light8080/
49 fixed: IE now enables interrupts after a 1-instruction delay
(it was enabling interrupts immediately)		 ja_rd 5416d 02h /light8080/
48 clarification of some terms in the comments ja_rd 5416d 18h /light8080/
47 edited the file list and added a few remarks ja_rd 5416d 18h /light8080/
46 minor change in signal color for better readability ja_rd 5416d 18h /light8080/
45 Added modelsim scripts for the test benches ja_rd 5416d 18h /light8080/
44 fixed error in RST test, added support for long intr tests
added a test of a 'long' intr pulse		 ja_rd 5416d 18h /light8080/
43 added a remark about the TASM source format ja_rd 5416d 18h /light8080/
42 test bench 1 regenerated with new template
added a test for 'long' intr pulses		 ja_rd 5416d 18h /light8080/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.