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Rev Log message Author Age Path
69 New simulation scripts for Modelsim in new separate directory.
Includes old test benches for CPU VHDL core and new test benches for SoC VHDL core		 ja_rd 4425d 15h /light8080/
68 Corrected ihex2vlog tool to enable explicit RAM declaration for Spartan 2. motilito 4436d 11h /light8080/
67 Corrected bugs in the Small-C compiler. motilito 4437d 13h /light8080/
66 Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code. motilito 4452d 11h /light8080/
65 Adding Verilog initial version to the svn.
Added the c80 Small-C compiler and AS80 assembler.		 motilito 4463d 18h /light8080/
64 BUG FIX: Flags CY and AC were not clear by logic instructions
Added new flag to microcode: clr_acy
Used new flag to clear AC and CY flags unconditonally
Modified microcode for XR*, OR* and AN* to use new flag
Modified microcode assembler to support new flag
Addex explaination of new flag to documentation
Old fix that worked only for XR* instructions removed
Test bench tb0 modified to test CY clearance minimally (AC untested!)
Pre-generated vhel test bench tb0 altered accordingly		 ja_rd 4472d 19h /light8080/
63 Modified syntax of ARGV parameter for compatibility to later versions of Perl ja_rd 4472d 19h /light8080/
62 Changed all hard tabs to spaces as preamble to a minor refactor ja_rd 4473d 04h /light8080/
61 Basic demo updated: main entity name changed to keep synthesis too happy ja_rd 4841d 05h /light8080/
60 Fixed nasty typo in pin constraints file (clock input) ja_rd 4845d 11h /light8080/

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