URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] [trunk/] - Rev 85

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Rev	Log message	Author	Age	Path
85	Moved all files common th the De-1 board demos to a new directory	ja_rd	4393d 17h	/light8080/trunk/
84	Added readme file to the 4kbasic code directory.	ja_rd	4393d 17h	/light8080/trunk/
83	4kbasic demo code deleted from old directory	ja_rd	4393d 17h	/light8080/trunk/
82	VHDL demo code reorganized: moved 4kbasic demo to new directory	ja_rd	4393d 17h	/light8080/trunk/
81	Removed backup file that shouldn't have been committed	ja_rd	4393d 17h	/light8080/trunk/
80	Improved usability of SoC (memory size calculation) Added comments to SoC code. Fixed starter kit board simulation test bench, added uart loopback	ja_rd	4393d 17h	/light8080/trunk/
79	DAA logic fixed and simplified	ja_rd	4393d 17h	/light8080/trunk/
78	Fixed a number of errors in the last refactor of the VHDL side of the project: - Path errors in the simulation scripts. - The reset pin in the C2SB mini-test-bench was not being driven. - The main vhdl test bench file was missing entirely. All of these errors due to not properly verifying the commit...	ja_rd	4399d 18h	/light8080/trunk/
77	Fixed a few mistakes in the last code reorganization. Mostly bad paths but also a broken comment in the UART source...	ja_rd	4400d 16h	/light8080/trunk/
76	Corrected some minor issues in the core description document.	motilito	4407d 08h	/light8080/trunk/
75	Updated file list	ja_rd	4410d 23h	/light8080/trunk/
74	Testbenches for VHDL core moved to sw/tb. Added a mini-demo for the VHDL SoC on the DE-1 dev board. Added a mini-testbench for the VHDL SoC.	ja_rd	4411d 00h	/light8080/trunk/
73	New tool for VHDL object code constant generation. Old VHDL template tool moved to tools directory.	ja_rd	4411d 00h	/light8080/trunk/
72	Added specs document for VHDL/Verilog CPU core	ja_rd	4411d 00h	/light8080/trunk/
71	IMSAI manual removed, no longer used	ja_rd	4411d 00h	/light8080/trunk/
70	Added new VHDL SoC for demonstration purposes	ja_rd	4411d 00h	/light8080/trunk/
69	New simulation scripts for Modelsim in new separate directory. Includes old test benches for CPU VHDL core and new test benches for SoC VHDL core	ja_rd	4411d 00h	/light8080/trunk/
68	Corrected ihex2vlog tool to enable explicit RAM declaration for Spartan 2.	motilito	4421d 19h	/light8080/trunk/
67	Corrected bugs in the Small-C compiler.	motilito	4422d 22h	/light8080/trunk/
66	Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code.	motilito	4437d 19h	/light8080/trunk/

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[/] [light8080/] [trunk/] - Rev 85

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