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Subversion Repositories light8080

[/] [light8080/] [trunk/] - Rev 89

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Rev	Log message	Author	Age	Path
69	New simulation scripts for Modelsim in new separate directory. Includes old test benches for CPU VHDL core and new test benches for SoC VHDL core	ja_rd	4423d 18h	/light8080/trunk/
68	Corrected ihex2vlog tool to enable explicit RAM declaration for Spartan 2.	motilito	4434d 14h	/light8080/trunk/
67	Corrected bugs in the Small-C compiler.	motilito	4435d 16h	/light8080/trunk/
66	Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code.	motilito	4450d 14h	/light8080/trunk/
65	Adding Verilog initial version to the svn. Added the c80 Small-C compiler and AS80 assembler.	motilito	4461d 22h	/light8080/trunk/
64	BUG FIX: Flags CY and AC were not clear by logic instructions Added new flag to microcode: clr_acy Used new flag to clear AC and CY flags unconditonally Modified microcode for XR, OR and AN* to use new flag Modified microcode assembler to support new flag Addex explaination of new flag to documentation Old fix that worked only for XR* instructions removed Test bench tb0 modified to test CY clearance minimally (AC untested!) Pre-generated vhel test bench tb0 altered accordingly	ja_rd	4470d 22h	/light8080/trunk/
63	Modified syntax of ARGV parameter for compatibility to later versions of Perl	ja_rd	4470d 22h	/light8080/trunk/
62	Changed all hard tabs to spaces as preamble to a minor refactor	ja_rd	4471d 07h	/light8080/trunk/
61	Basic demo updated: main entity name changed to keep synthesis too happy	ja_rd	4839d 09h	/light8080/trunk/
60	Fixed nasty typo in pin constraints file (clock input)	ja_rd	4843d 14h	/light8080/trunk/

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