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Rev Log message Author Age Path
89 Specs document updated ja_rd 4346d 16h /light8080/trunk/doc/
76 Corrected some minor issues in the core description document. motilito 4400d 05h /light8080/trunk/doc/
72 Added specs document for VHDL/Verilog CPU core ja_rd 4403d 20h /light8080/trunk/doc/
71 IMSAI manual removed, no longer used ja_rd 4403d 20h /light8080/trunk/doc/
64 BUG FIX: Flags CY and AC were not clear by logic instructions
Added new flag to microcode: clr_acy
Used new flag to clear AC and CY flags unconditonally
Modified microcode for XR*, OR* and AN* to use new flag
Modified microcode assembler to support new flag
Addex explaination of new flag to documentation
Old fix that worked only for XR* instructions removed
Test bench tb0 modified to test CY clearance minimally (AC untested!)
Pre-generated vhel test bench tb0 altered accordingly
ja_rd 4451d 00h /light8080/trunk/doc/
31 New directory structure. root 5520d 10h /light8080/trunk/doc/
9 Design notes now done with LaTeX, OpenOffice source removed ja_rd 5659d 16h /trunk/doc/
8 LaTeX source for the design notes ja_rd 5659d 16h /trunk/doc/
7 Minor edits and clarifications,
plus document is now generated with LaTeX instead of OpenOffice
ja_rd 5659d 16h /trunk/doc/
2 initial commit ja_rd 6010d 23h /trunk/doc/

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