URL https://opencores.org/ocsvn/light8080/light8080/trunk

Subversion Repositories light8080

[/] [light8080/] [trunk/] [doc/] - Rev 79

Rev	Log message	Author	Age	Path
76	Corrected some minor issues in the core description document.	motilito	4846d 18h	/light8080/trunk/doc/
72	Added specs document for VHDL/Verilog CPU core	ja_rd	4850d 10h	/light8080/trunk/doc/
71	IMSAI manual removed, no longer used	ja_rd	4850d 10h	/light8080/trunk/doc/
64	BUG FIX: Flags CY and AC were not clear by logic instructions Added new flag to microcode: clr_acy Used new flag to clear AC and CY flags unconditonally Modified microcode for XR, OR and AN* to use new flag Modified microcode assembler to support new flag Addex explaination of new flag to documentation Old fix that worked only for XR* instructions removed Test bench tb0 modified to test CY clearance minimally (AC untested!) Pre-generated vhel test bench tb0 altered accordingly	ja_rd	4897d 13h	/light8080/trunk/doc/
31	New directory structure.	root	5966d 23h	/light8080/trunk/doc/
9	Design notes now done with LaTeX, OpenOffice source removed	ja_rd	6106d 05h	/trunk/doc/
8	LaTeX source for the design notes	ja_rd	6106d 05h	/trunk/doc/
7	Minor edits and clarifications, plus document is now generated with LaTeX instead of OpenOffice	ja_rd	6106d 05h	/trunk/doc/
2	initial commit	ja_rd	6457d 12h	/trunk/doc/