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[/] [light8080/] [trunk] - Rev 80

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Rev	Log message	Author	Age	Path
80	Improved usability of SoC (memory size calculation) Added comments to SoC code. Fixed starter kit board simulation test bench, added uart loopback	ja_rd	4414d 03h	/light8080/trunk
79	DAA logic fixed and simplified	ja_rd	4414d 03h	/light8080/trunk
78	Fixed a number of errors in the last refactor of the VHDL side of the project: - Path errors in the simulation scripts. - The reset pin in the C2SB mini-test-bench was not being driven. - The main vhdl test bench file was missing entirely. All of these errors due to not properly verifying the commit...	ja_rd	4420d 04h	/light8080/trunk
77	Fixed a few mistakes in the last code reorganization. Mostly bad paths but also a broken comment in the UART source...	ja_rd	4421d 02h	/light8080/trunk
76	Corrected some minor issues in the core description document.	motilito	4427d 18h	/light8080/trunk
75	Updated file list	ja_rd	4431d 09h	/light8080/trunk
74	Testbenches for VHDL core moved to sw/tb. Added a mini-demo for the VHDL SoC on the DE-1 dev board. Added a mini-testbench for the VHDL SoC.	ja_rd	4431d 10h	/light8080/trunk
73	New tool for VHDL object code constant generation. Old VHDL template tool moved to tools directory.	ja_rd	4431d 10h	/light8080/trunk
72	Added specs document for VHDL/Verilog CPU core	ja_rd	4431d 10h	/light8080/trunk
71	IMSAI manual removed, no longer used	ja_rd	4431d 10h	/light8080/trunk
70	Added new VHDL SoC for demonstration purposes	ja_rd	4431d 10h	/light8080/trunk
69	New simulation scripts for Modelsim in new separate directory. Includes old test benches for CPU VHDL core and new test benches for SoC VHDL core	ja_rd	4431d 10h	/light8080/trunk
68	Corrected ihex2vlog tool to enable explicit RAM declaration for Spartan 2.	motilito	4442d 05h	/light8080/trunk
67	Corrected bugs in the Small-C compiler.	motilito	4443d 08h	/light8080/trunk
66	Adding interrupt example code to the Verilog implementation. An interrupt controller was added to the sample SOC module and a sample code was added to the "hello.c" example code.	motilito	4458d 06h	/light8080/trunk
65	Adding Verilog initial version to the svn. Added the c80 Small-C compiler and AS80 assembler.	motilito	4469d 13h	/light8080/trunk
64	BUG FIX: Flags CY and AC were not clear by logic instructions Added new flag to microcode: clr_acy Used new flag to clear AC and CY flags unconditonally Modified microcode for XR, OR and AN* to use new flag Modified microcode assembler to support new flag Addex explaination of new flag to documentation Old fix that worked only for XR* instructions removed Test bench tb0 modified to test CY clearance minimally (AC untested!) Pre-generated vhel test bench tb0 altered accordingly	ja_rd	4478d 13h	/light8080/trunk
63	Modified syntax of ARGV parameter for compatibility to later versions of Perl	ja_rd	4478d 13h	/light8080/trunk
62	Changed all hard tabs to spaces as preamble to a minor refactor	ja_rd	4478d 23h	/light8080/trunk
61	Basic demo updated: main entity name changed to keep synthesis too happy	ja_rd	4847d 00h	/light8080/trunk

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[/] [light8080/] [trunk] - Rev 80

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