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Rev Log message Author Age Path
27 Brief instructions for batch script ja_rd 5594d 12h /
26 Builds test bench from vhdl template and assembly source
relies on TASM to do the assembly
ja_rd 5594d 12h /
25 Moved from /util
Added comments and generally improved options
ja_rd 5594d 12h /
24 Totally changed -- tests interrupts using simulated interrupt controller in hdl test bench
Code reformatted for TASM
ja_rd 5594d 12h /
23 Code reformatted for TASM ja_rd 5594d 12h /
22 Totally changed -- vhdl code generated from a template
Interrupts tested from software using a simulated interrupt controller
ja_rd 5594d 12h /
21 Totally changed -- vhdl code generated from a template ja_rd 5594d 12h /
20 VHDL template for test benches ja_rd 5594d 13h /
19 Fixed a bug (intr pulses longer than 1 clock cycle failed in some circumstances)
Added an output to the core to mark the fetch cycle of all instructions
Started to add timing diagrams
ja_rd 5594d 13h /
18 Uncluttered the signal display a bit ja_rd 5594d 13h /
17 Comments added ja_rd 5680d 15h /
16 adding LST filed generated by TASM ja_rd 5680d 16h /
15 Names and contents of some files changed ja_rd 5680d 16h /
14 Syntax changed from CP/M ASM to DOS TASM
Success code changed
ja_rd 5680d 16h /
13 Minor changes in embedded code changed (success code now stands out better visually)
Comments added explaining the TB mechanincs
ja_rd 5680d 16h /
12 Minor changes in embedded code changed (success code now stands out better visually) ja_rd 5680d 16h /
11 typos fixed ja_rd 5680d 16h /
10 minor edits, comments clarified ja_rd 5708d 06h /
9 Design notes now done with LaTeX, OpenOffice source removed ja_rd 5713d 13h /
8 LaTeX source for the design notes ja_rd 5713d 13h /

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